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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7822/ad7825/ad7829 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 3 v/5 v, 2 msps, 8-bit, 1-, 4-, 8-channel sampling adcs functional block diagram convst db0 db7 8-bit half flash adc parallel port vref in /ref out eoc rd cs agnd v mid a0* a1* a2* v in1 comp pd * 2.5v ref v dd control logic dgnd input mux v in2* v in3* v in4* v in5* v in6* v in7* v in8* t/h *a0, a1 *a2 * pd *v in2 to v in4 *v in4 to v in8 ad7825/ad7829 ad7829 ad7822/ad7825 ad7825/ad7829 ad7829 buf features 8-bit half-flash adc with 420 ns conversion time 1, 4 and 8 single-ended analog input channels available with input offset adjust on-chip track-and-hold snr performance given for input frequencies up to 10 mhz on-chip reference (2.5 v) automatic power-down at the end of conversion wide operating supply range 3 v 6 10% and 5 v 6 10% input ranges 0 v to 2 v p-p, v dd = 3 v 6 10% 0 v to 2.5 v p-p, v dd = 5 v 6 10% flexible parallel interface with eoc pulse to allow stand-alone operation applications data acquisition systems, dsp front ends disk drives mobile communication systems, subsampling applications general description the ad7822, ad7825, and ad7829 are high speed, 1-, 4-, and 8-channel, microprocessor-compatible, 8-bit analog-to-digital converters with a maximum throughput of 2 msps. the ad7822, ad7825, and ad7829 contain an on-chip reference of 2.5 v (2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash adc and a high speed parallel interface. the converters can operate from a single 3 v 10% and 5 v 10% supply. the ad7822, ad7825, and ad7829 combine the convert start and power-down functions at one pin, i.e., the convst pin. this allows a unique automatic power-down at the end of a conversion to be implemented. the logic level on the convst pin is sampled after the end of a conversion when an eoc (end of conversion) signal goes high, and if it is logic low at that point, the adc is powered down. the ad7822 and ad7825 also have a separate power-down pin. (see operating modes section of the data sheet.) the parallel interface is designed to allow easy interfacing to microprocessors and dsps. using only address decoding logic, the parts are easily mapped into the microprocessor address space. the eoc pulse allows the adcs to be used in a stand- alone manner. (see parallel interface section of the data sheet.) the ad7822 and ad7825 are available in a 20-/24-lead 0.3" wide, plastic dual-in-line package (dip), a 20-/24-lead small outline ic (soic) and a 20-/24-lead thin shrink small outline package (tssop). the ad7829 is available in a 28-lead 0.6" wide, plastic dual-in-line package (dip), a 28-lead small outline ic (soic) and in a 28-lead thin shrink small outline package (tssop). product highlights 1. fast conversion time the ad7822, ad7825, and ad7829 have a conversion time of 420 ns. faster conversion times maximize the dsp pro- cessing time in a real time system. 2. analog input span adjustment the v mid pin allows the user to offset the input span. this feature can reduce the requirements of single supply op amps and take into account any system offsets. 3. fpbw (full power bandwidth) of track and hold the track-and-hold amplifier has an excellent high frequency performance. the ad7822, ad7825, and ad7829 are capable of converting full-scale input signals up to a fre- quency of 10 mhz. this makes the parts ideally suited to subsampling applications. 4. channel selection channel selection is made without the necessity of writing to the part.
C2C rev. a ad7822/ad7825/ad7829Cspecifications parameter version b unit test condition/comment dynamic performance f in = 30 khz. f sample = 2 mhz signal to (noise + distortion) ratio 1 48 db min total harmonic distortion 1 C55 db max peak harmonic or spurious noise 1 C55 db max intermodulation distortion 1 fa = 27.3 khz, fb = 28.3 khz 2nd order terms C65 db typ 3rd order terms C65 db typ channel-to-channel isolation 1 C70 db typ f in = 20 khz dc accuracy resolution 8 bits minimum resolution for which no missing codes are guaranteed 8 bits integral nonlinearity (inl) 1 0.75 lsb max differential nonlinearity (dnl) 1 0.75 lsb max gain error 1 2lsb max gain error match 1 0.1 lsb typ offset error 1 1lsb max offset error match 1 0.1 lsb typ analog inputs 2 see analog input section v dd = 5 v 10% input voltage span = 2.5 v v in1 to v in8 input voltage v dd v max 0v min v mid input voltage v dd C 1.25 v max default v mid = 1.25 v 1.25 v min v dd = 3 v 10% input voltage span = 2 v v in1 to v in8 input voltage v dd v max 0v min v mid input voltage v dd C 1 v max default v mid = 1 v 1v min v in input leakage current 1 m a max v in input capacitance 15 pf max v mid input impedance 6 k w typ reference input v ref in / out input voltage range 2.55 v max 2.5 v + 2% 2.45 v min 2.5 v C 2% input current 1 m a typ 100 m a max on-chip reference nominal 2.5 v reference error 50 mv max temperature coefficient 50 ppm/ c typ logic inputs input high voltage, v inh 2.4 v min v dd = 5 v 10% input low voltage, v inl 0.8 v max v dd = 5 v 10% input high voltage, v inh 2v minv dd = 3 v 10% input low voltage, v inl 0.4 v max v dd = 3 v 10% input current, i in 1 m a max typically 10 na, v in = 0 v to v dd input capacitance, c in 10 pf max logic outputs output high voltage, v oh i source = 200 m a 4v minv dd = 5 v 10% 2.4 v min v dd = 3 v 10% output low voltage, v ol i sink = 200 m a 0.4 v max v dd = 5 v 10% 0.2 v max v dd = 3 v 10% high impedance leakage current 1 m a max high impedance capacitance 10 pf max (v dd = 3 v 6 10%, v dd = 5 v 6 10%, gnd = 0 v, v ref in/out = 2.5 v. all specifications C40 8 c to +85 8 c unless otherwise noted.)
parameter version b unit test condition/comment conversion rate track/hold acquisition time 200 ns max see functional description section conversion time 420 ns max power supply rejection v dd 10% 1 lsb max power requirements v dd 4.5 v min 5 v 10%. for specified performance 5.5 v max v dd 2.7 v min 3 v 10%. for specified performance 3.3 v max i dd normal operation 12 ma max 8 ma typically power-down 5 m a max logic inputs = 0 v or v dd 0.2 m a typ power dissipation v dd = 3 v normal operation 36 mw max typically 24 mw power-down 200 ksps 9.58 mw max 1 msps 47.88 mw max notes 1 see terminology section of this data sheet. 2 refer to the analog input section for an explanation of the analog input(s). specifications subject to change without notice. ordering guide linearity package package model error description option ad7822bn 0.75 lsb plastic dip n-20 ad7822br 0.75 lsb small outline ic r-20 ad7822bru 0.75 lsb thin shrink small ru-20 outline (tssop) AD7825BN 0.75 lsb plastic dip n-24 ad7825br 0.75 lsb small outline ic r-24 ad7825bru 0.75 lsb thin shrink small ru-24 outline (tssop) ad7829bn 0.75 lsb plastic dip n-28 ad7829br 0.75 lsb small outline ic r-28 ad7829bru 0.75 lsb thin shrink small ru-28 outline (tssop) +2.1v i ol 200 m a 200 m a i oh to output pin c l 50pf figure 1. load circuit for access time and bus relinquish time ad7822/ad7825/ad7829 C3C rev. a
ad7822/ad7825/ad7829 C4C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7822/ad7825/ad7829 features proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing characteristics 1, 2 parameter 5 v 6 10% 3 v 6 10% unit conditions/comments t 1 420 420 ns max conversion time. t 2 20 20 ns min minimum convst pulsewidth. t 3 30 30 ns min minimum time between the rising edge of rd and next falling edge of convert start. t 4 110 110 ns max eoc pulsewidth. 70 70 ns min t 5 10 10 ns max rd rising edge to eoc pulse high. t 6 0 0 ns min cs to rd setup time. t 7 0 0 ns min cs to rd hold time. t 8 30 30 ns min minimum rd pulsewidth. t 9 3 10 20 ns max data access time after rd low. t 10 4 5 5 ns min bus relinquish time after rd high. 20 20 ns max t 11 10 10 ns min address setup time before falling edge of rd . t 12 15 15 ns min address hold time after falling edge of rd . t 13 200 200 ns min minimum time between new channel selection and convert start. t power up 25 25 m s typ power-up time from rising edge of convst using on-chip reference. t power up 11 m s max power-up time from rising edge of convst using external 2.5 v reference. notes 1 sample tested to ensure compliance. 2 see figures 20, 21 and 22. 3 measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v with v dd = 5 v 10%, and time required for an out- put to cross 0.4 v or 2.0 v with v dd = 3 v 10%. 4 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 10 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. specifications subject to change without notice. absolute maximum ratings * (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v analog input voltage to agnd v in1 to v in8 . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v reference input voltage to agnd . . . C0.3 v to v dd + 0.3 v v mid input voltage to agnd . . . . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c plastic dip package, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 105 c/w lead temperature, (soldering, 10 sec) . . . . . . . . . . . 260 c soic package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220 c tssop package, power dissipation . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 128 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kv * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (v ref in/out = 2.5 v. all specifications C40 8 c to +85 8 c unless otherwise noted) warning! esd sensitive device
ad7822/ad7825/ad7829 C5C rev. a pin function descriptions mnemonic description v in1 to v in8 analog input channels. the ad7822 has a single input channel; the ad7825 and ad7829 have four and eight analog input channels respectively. the inputs have an input span of 2.5 v and 2 v depending on the sup- ply voltage (v dd ). this span may be centered anywhere in the range agnd to v dd using the v mid pin. the default input range (v mid unconnected) is agnd to 2 v (v dd = 3 v 10%) or agnd to 2.5 v (v dd = 5 v 10%). see analog input section of the data sheet for more information. v dd positive supply voltage, 3 v 10% and 5 v 10%. agnd analog ground. ground reference for track/hold, comparators, reference circuit and multiplexer. dgnd digital ground. ground reference for digital circuitry. convst logic input signal. the convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. the falling edge of this signal places the track/hold in hold mode. the track/hold goes into track mode again 120 ns after the start of a conversion. the state of the convst signal is checked at the end of a conversion. if it is logic low, the ad7822/ad7825/ad7829 will power down. (see operating mode section of the data sheet.) eoc logic output. the end of conversion signal indicates when a conversion has finished. the signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (see parallel inter- face section of this data sheet.) cs logic input signal. the chip select signal is used to enable the parallel port of the ad7822, ad7825, and ad7829. this is necessary if the adc is sharing a common data bus with another device. pd logic input. the power-down pin is present on the ad7822 and ad7825 only. bringing the pd pin low places the ad7822 and ad7825 in power-down m ode. the adcs will power-up when pd is brought logic high again. rd logic input signal. the read signal is used to take the output buffers out of their high impedance state and drive data onto the data bus. the signal is internally gated with the cs signal. both rd and cs must be logic low to enable the data bus. a0Ca2 channel address inputs. the address of the next multiplexer channel must be present on these inputs when the rd signal goes low. db0Cdb7 data output lines. they are normally held in a high impedance state. data is driven onto the data bus when both rd and cs go active low. v ref in / out analog input and output. an external reference can be connected to the ad7822, ad7825, and ad7829 at this pin. the on-chip reference is also available at this pin. pin configurations dip/soic/tssop 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad7822 nc = no connect db2 db6 db5 db4 db3 db1 db0 convst v dd agnd db7 cs rd dgnd eoc pd nc v in1 v mid v ref 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad7825 db2 db6 db5 db4 db3 db1 db0 convst v dd agnd db7 cs rd dgnd eoc a1 a0 v in1 v mid v ref pd v in4 v in2 v in3 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad7829 db2 db6 db5 db4 db3 db1 db0 convst v dd agnd db7 cs rd dgnd eoc a2 a1 v in1 v mid v ref a0 v in8 v in7 v in6 v in2 v in5 v in4 v in3
ad7822/ad7825/ad7829 C6C rev. a terminology signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to -( noise + distortion ) = (6.02 n + 1.76) db thus, for an 8-bit converter, this is 50 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7822/ad7825/ad7829 it is defined as: thd ( db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7822/ad7825/ad7829 are tested using the ccif stan- dard where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodula- tion distortion is as per the thd specification w here it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full-scale 20 khz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. the figure given is the worst case across all four or eight chan- nels of the ad7825 and ad7829 respectively. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the 128th code transition (01111111) to (10000000) from the ideal, i.e., v mid . offset error match the difference in offset error between any two channels. zero-scale error the deviation of the first code transition (00000000) to (00000001) from the ideal, i.e., v mid C 1.25 v + 1 lsb (v dd = 5 v 10%), or v mid C 1.0 v + 1 lsb (v dd = 3 v 10%). full-scale error the deviation of the last code transition (11111110) to (11111111) from the ideal, i.e., v mid + 1.25 v C 1 lsb (v dd = 5 v 10%), or v mid + 1.0 v C 1 lsb (v dd = 3 v 10%). gain error the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., v ref C 1 lsb, after the off- set error has been adjusted out. gain error match the difference in gain error between any two channels. track/hold acquisition time the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the point at which the track/hold returns to track mode. this happens approxi- mately 120 ns after the falling edge of convst . it also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected v in input of the ad7822/ ad7825/ad7829. it means that the user must wait for the dura- tion of the track/hold acquisition time after a channel change/step input change to v in before starting another conversion, to ensure that the part operates to specification. psr (power supply rejection) variations in power supply will affect the full-scale transition, but not the converters linearity. power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. circuit description the ad7822, ad7825, and ad 7829 consist of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. these devices use a half-flash conversion technique where one 4-bit flash adc is used to achieve an 8-bit result. the 4-bit flash adc contains a sampling capacitor followed by fifteen comparators that compare the unknown input to a reference ladder to achieve a 4-bit result. this first flash, i.e., coarse con- version, provides the 4 msbs. for a full 8-bit reading to be realized, a second flash, i.e., a fine conversion, must be per- formed to provide the 4 lsbs. the 8-bit word is then placed on the data output bus.
ad7822/ad7825/ad7829 C7C rev. a figures 2 and 3 below show simplified schematics of the adc. when the adc starts a conversion, the track and hold goes into hold mode and holds the analog input for 120 ns. this is the acquisition phase as shown in figure 2, when switch 2 is in position a. at the point when the track and hold returns to its track mode, this signal is sampled by the sampling capacitor as switch 2 moves into position b. the first flash occurs at this instant and is then followed by the second flash. typically, the first flash is complete after 100 ns, i.e., at 220 ns, while the end of the second flash and hence the 8-bit c onversion result is available at 330 ns. as shown in figure 4, the track-and-hold returns to track mode after 120 ns, and starts the next acquisi- tion before the end of the current conversion. figure 6 shows the adc transfer function. timing and control logic r1 hold sampling capacitor a b sw2 r16 r15 r14 r13 t/h 1 output register output drivers v in reference d7 d6 d5 d4 d3 d2 d1 d0 decode logic 14 15 13 1 figure 2. adc acquisition phase timing and control logic r1 hold sampling capacitor a b sw2 r16 r15 r14 r13 t/h 1 output register output drivers v in reference d7 d6 d5 d4 d3 d2 d1 d0 decode logic 14 15 13 1 figure 3. adc conversion phase hold hold 120ns convst eoc cs rd db0-db7 t 2 t 1 t 3 track track valid data figure 4. track-and-hold timing typical connection diagram figure 5 shows a typical connection diagram for the ad7822, ad7825, and ad7829. the agnd and dgnd are connected together at the device for good noise suppression. the parallel interface is implemented using an 8-bit data bus. the end of conversion signal ( eoc ) idles high, the falling edge of convst initiates a conversion and at the end of conversion the falling edge of eoc is used to initiate an interrupt service routine (isr) on a microprocessor. (see parallel interface section for more details.) v ref and v mid are connected to voltage source such as the ad780, while v dd is connected to a voltage source that can vary from 4.5 v to 5.5 v. (see table i in analog input section.) when v dd is first connected, the ad7822, ad7825, and ad7829 power up in a low current mode, i.e., power-down, with the default logic level on the eoc pin on the ad7822 and ad7825 equal to a low. ensure the convst line is not floating when v dd is applied, as this could put the ad7822/ad7825/ ad7829 into an unknown state. a rising edge on the convst pin will cause the ad7829 to fully power up while a rising edge on the pd pin will cause the ad7822 and ad7825 to fully power up. for applications where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance. (see power-down options section of the data sheet.) supply +4.5v to +5.5v 10 m f 0.1 m f v dd v ref v mid v in1 1.25v to 3.75v input v in2 v in4(8) agnd db0-db7 eoc rd cs convst a0 a1 a2 pd parallel interface m c/ m p ad7822/ ad7825/ ad7829 dgnd 2.5v ad780 figure 5. typical connection diagram
ad7822/ad7825/ad7829 C8C rev. a adc transfer function the output coding of the ad7822, ad7825, and ad7829 is straight binary. the designed code transitions occur at succes- sive integer lsb values (i.e., 1 lsb, 2 lsbs, etc.). the lsb size is = v ref /256 (v dd = 5 v) or the lsb size = (0.8 v ref )/256 (v dd = 3 v). the ideal transfer characteristic for the ad7822, ad7825, and ad7829 is shown in figure 6, below. 11111111 111...110 111...000 10000000 000...111 000...010 00000000 (v dd = 5v) 1lsb = v ref /256 (v dd = 3v) 1lsb = 0.8v ref /256 000...001 adc code 1lsb v mid (v dd = 5v) v mid C1.25v (v dd = 3v) v mid C1v v mid +1.25vC1lsb v mid +1vC1lsb analog input voltage figure 6. transfer characteristic analog input the ad7822 has a single input channel and the ad7825 and ad7829 have four and eight input channels respectively. each input channel has an input span of 2.5 v or 2.0 v, depending on the supply voltage (v dd ). this input span is autom atically set up by an on-chip v dd detector circuit. 5 v operation of the adcs is detected when v dd exceeds 4.1 v and 3 v operation is detected when v dd falls below 3.8 v. this circuit also possesses a degree of glitch rejection; for example, a glitch from 5.5 v to 2.7 v up to 60 ns wide will not trip the v dd detector. the v mid pin is used to center this input span anywhere in the range agnd to v dd . if no input voltage is applied to v mid , i.e., if v mid is left unconnected, the default input range is agnd to 2.0 v (v dd = 3 v 10%) i.e., centered about 1.0 v, or agnd to 2.5 v (v dd = 5 v 10%) i.e., centered about 1.25 v. if, however, an external v mid is applied, the analog input range will be from v mid C 1.0 v to v mid + 1.0 v (v dd = 3 v 10%), or from v mid C 1.25 v to v mid + 1.25 v (v dd = 5 v 10%). the range of values of v mid that can be applied depends on the value of v dd . for v dd = 3 v 10%, the range of values that can be applied to v mid is from 1.0 v to v dd C 1.0 v and is 1.25 v to v dd C 1.25 v when v dd = 5 v 10%. table i shows the rel- evant ranges of v mid and the input span for various values of v dd . figure 7 illustrates the input signal range available with various values of v mid . table i. v mid v mid ext v mid ext v dd internal max v in span min v in span 5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5 5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5 4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5 3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0 3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0 2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0 5v 4v 3v 2v 1v v dd = 5v input signal range for various v mid v mid = n/c (1.25v) v mid = 2.5v v mid = 3.75v 3v 2v 1v v dd = 3v input signal range for various v mid v mid = n/c (1v) v mid = 1.5v v mid = 2v figure 7. analog input span variation with v mid v mid may be used to remove offsets in a system by applying the offset to the v mid pin as shown in figure 8, or it may be used to accommodate bipolar signals by applying v mid to a level-shifting circuit before v in , as shown in figure 9. when v mid is being driven by an external source, the source may be directly tied to the level-shifting circuitry, see figure 9; however, if the internal v mid , i.e., the default value, is being used as an output, it must be buffered before applying it to the level-shifting circuitry as the v mid pin has an impedance of approximately 6 k w , see figure 10. v in v mid ad7822/ ad7825/ ad7829 v mid v in v mid figure 8. removing offsets using v mid
ad7822/ad7825/ad7829 C9C rev. a v ref v mid v in r3 r4 r2 r1 v v 0v v in 0v 2.5v ad7822/ ad7825/ ad7829 2.5v figure 9. accommodating bipolar signals using external v mid r2 v ref v mid v in external 2.5v r3 r4 r1 v v 0v v in 0v v mid ad7822/ ad7825/ ad7829 figure 10. accommodating bipolar signals using internal v mid note: although there is a v ref pin from which a voltage reference of 2.5 v may be sourced, or to which an external ref- erence may be applied, this does not provide an option of varying the value of the voltage reference. as stated in the specifications for the ad7822, ad7825, and ad7829, the input voltage range at this pin is 2.5 v 2%. analog input structure figure 11 shows an equivalent circuit of the analog input structure of the ad7822, ad 7825, and the ad7829. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 20 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. how- ever, it is worth noting that a small amount of current (1 ma) being conducted into the substrate due to an over voltage on an unselected channel, can cause inaccurate conversions on a se- lected channel. the capacitor c2 in figure 11 is typically about 4 pf and can be primarily attributed to pin capacitance. the resistor, r1, is a lumped component made up of the on resis- tance of several components, including that of the multi plexer and the track and hold. this resistor is typically about 310 w . the capacitor c1 is the track-and-hold capacitor and has a ca- pacitance of 0.5 pf. switch 1 is the track-and-hold switch, while switch 2 is that of the sampling capacitor as shown in figures 2 and 3. when in track phase, switch 1 is closed and switch 2 is in position a; when in hold mode, switch 1 opens while switch 2 remains in position a. the track-and-hold remains in hold mode for 120 nssee circuit description, after which it returns to track mode and the adc enters its conversion phase. at this point switch 1 opens and switch 2 moves to position b. at the end of the conversion switch 2 moves back to position a. v in c2 4pf d1 d2 r1 310 v sw1 c1 0.5pf a b sw2 v dd figure 11. equivalent analog input circuit analog input selection on power-up, the default v in selection is v in1 . when returning to normal operation from power-down, the v in selected will be the same one that was selected prior to power-down being initiated. table ii below shows the multiplexer address corresponding to each analog input from v in1 to v in4(8) for the ad7825 or ad7829. table ii. a2 a1 a0 analog input selected 00 0 v in1 00 1 v in2 01 0 v in3 01 1 v in4 10 0 v in5 10 1 v in6 11 0 v in7 11 1 v in8 channel selection on the ad7825 and ad7829 is made without the necessity of a write operation. the address of the next channel to be converted is latched at the start of the current read operation, as shown in figure 12. this allows for improved throughput rates in channel hopping applications.
ad7822/ad7825/ad7829 C10C rev. a convst db0-db7 a0-a2 eoc cs rd t 2 t 1 t 3 t 13 valid data address channel y track chx track chx hold chx track chy hold chy 120ns figure 12. channel hopping timing there is a minimum time delay between the falling edge of rd and the next falling edge of the convst signal, t 13 . this is the minimum acquisition time required of the track-and-hold in order to maintain 8-bit performance. figure 13 shows the typical performance of the ad7825 when channel hopping for various acquisition times. these results were obtained using an external reference and internal v mid while channel hopping between v in1 and v in4 with 0 v on channel 4 and 0.5 v on channel 1. acquisition time C ns 8 5 500 10 200 enob 100 50 40 30 20 15 7.5 7 6.5 6 5.5 8.5 figure 13. effective number of bits vs. acquisition time for the ad7825 the on-chip track-and-hold can accommodate input frequen- cies to 10 mhz, making the ad7822, ad7825, and ad7829 ideal for subsampling applications. when the ad7825 is con- verting a 10 mhz input signal at a sampling rate of 2 msps, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dbs as shown in figure 14. input frequency C mhz 50 38 0.2 10 1 snr C db 34568 48 46 44 42 40 f sample = 2mhz figure 14. snr vs. input frequency on the ad7825 power-up times the ad7822/ad7825/ad7829 have a 1 m s power-up time when using an external reference and a 25 m s power-up time when using the on-chip reference. when v dd is first connected, the ad7822, ad7825, and ad7829 are in a low current mode of operation. ensure that the convst line is not floating when v dd is applied, as this could put the ad7822/ad7825/ad7829 into an unknown state. in order to carry out a conversion the ad7822, ad7825, and ad7829 must first be powered up. the ad7829 is powered up by a rising edge on the convst pin and a conversion is initiated on the falling edge of convst . figure 15 shows how to power up the ad7829 when v dd is first connected or after the ad7829 has been powered down using the convst pin when using either the on-chip, or an external, reference. when using an external reference, the falling edge of convst may occur before the required power-up time has elapsed; however, the conversion will not be initiated on the fall- ing edge of convst but rather at the moment when the part has completely powered up, i.e., after 1 m s. if the falling edge of convst occurs after the required power-up time has elapsed, then it is upon this falling edge that a conversion is initiated. when using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 m s before initiating a conversion; i.e., a falling edge on convst may not occur before the required power-up time has elapsed, when v dd is first connected or after the ad7829 has been powered down using the convst pin as shown in figure 15. v dd t power-up 1 m s convst v dd convst t power-up 25 m s conversion initiated here conversion initiated here external reference on-chip reference figure 15. ad7829 power-up time
ad7822/ad7825/ad7829 C11C rev. a figure 16 shows how to power up the ad7822 or ad7825 when v dd is first connected or after the adcs have been powered down using the pd pin, or the convst pin, with either the on-chip or an external reference. when the supplies are first connected or after the part has been powered down by the pd pin, only a rising edge on the pd pin will cause the part to power up. when the part has been powered down using the convst pin, a rising edge on either the pd pin or the convst pin will power the part up again. as with the ad7829, when using an external reference with the ad7822 or ad7825, the falling edge of convst may occur before the required power-up time has elapsed, however, if this is the case, the conversion will not be i nitiated on the falling edge of convst , but rather at the moment when the part has powered up completely, i.e., after 1 m s. if the falling edge of convst occurs after the required power-up time has elapsed, it is upon this falling edge that a conversion is initiated. when using the on-chip reference it is necessary to wait the required power- up time of approximately 25 m s before initiating a conversion; i.e., a falling edge on convst may not occur before the required power-up time has elapsed, when supplies are first connected to the ad7822 or ad7825, or when the adcs have been powered down using the pd pin or the convst pin as shown in figure 16. v dd pd convst t power-up 1 m s t power-up 1 m s conversion initiated here conversion initiated here v dd pd convst t power-up 25 m s t power-up 25 m s conversion initiated here conversion initiated here external reference on-chip reference figure 16. ad7822/ad7825 power-up time power vs. throughput superior power performance can be achieved by using the auto- matic power-down (mode 2) at the end of a conversionsee operating modes section of the data sheet. figure 17 shows how the automatic power-down is implemented using the convst signal to achieve the optimum power per- formance for the ad7822, ad7825, and ad7829. the duration of the convst pulse is set to be equal to or less than the power-up time of the devicessee operating modes section. as the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. t power-up 1 m s 330ns t convert power-down t cycle 10 m s @ 100ksps convst figure 17. automatic power-down for example, if the ad7822 is operated in a continuous sam- pling mode, with a throughput rate of 100 ksps and using an external reference, the power consumption is calculated as fol- lows. the power dissipation during normal opera tion is 36 mw, v dd = 3 v. if the power-up time is 1 m s and the conversion time is 330 ns (@ +25 c), the ad7822 can be said to dissipate 36 mw for 1.33 m s (worst case) during each conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 m s and the average power dissipated during each cycle is (1.33/10) (36 mw) = 4.79 mw. figure 18 shows the power vs. throughput rate for automatic full power-down. throughput C ksps 100 10 0 0 500 100 power C mw 1 200 300 400 0.1 50 150 250 350 450 figure 18. ad7822/ad7825/ ad7829 power vs. throughput frequency C khz 0 C10 C80 db C40 C50 C60 C70 C20 C30 0 113 142 170 198 227 255 283 312 340 368 396 425 453 481 510 538 566 595 623 651 680 708 736 765 793 821 850 878 906 935 963 28 57 85 991 2048 point fft sampling 2msps f in = 200khz figure 19. ad7822/ad7825/ad7829 snr
ad7822/ad7825/ad7829 C12C rev. a operating modes the ad7822, ad7825, and ad7829 have two possible modes of operation, depending on the state of the convst pulse approximately 100 ns after the end of a conversion, i.e., upon the rising edge of the eoc pulse. mode 1 operation (high speed sampling) when the ad7822, ad7825, and ad7829 are operated in mode 1 they are not powered-down between conversions. this mode of operation allows high throughput rates to be achieved. figure 20 shows how this optimum throughput rate is achieved by bringing convst high before the end of a conversion, i.e., before the eoc pulses low. when operating in this mode a new conversion should not be initiated until 30 ns after the end of a read operation. this is to allow the track/hold to acquire the analog signal to 0.5 lsb accuracy. mode 2 operation (automatic power-down) when the ad7822, ad7825, and ad7829 are operated in mode 2 (see figure 21), they automatically power down at the end of a conversion. the convst signal is brought low to ini- tiate a conversion and is left logic low until after the eoc goes high, i.e., approximately 100 ns after the end of the conversion. the state of the convst signal is sampled at this point (i.e., 530 ns maximum after convst falling edge) and the ad7822, ad7825, and ad7829 will power down as long as convst is low. the adc is pow ered up again on the rising edge of the convst signal. superior power performance can be achieved in this mode of operation by only powering up the ad7822, ad7825, and ad7829 to carry out a conversion. the parallel interface of the ad7822, ad7825, and ad7829 is still fully operational while the adcs are powered down. a read may occur while the part is powered down, and so it does not necessarily need to be placed within the eoc pulse as shown in figure 21. t 2 t 1 t 3 valid data convst eoc cs rd db0-db7 track hold track hold 120ns figure 20. mode 1 operation convst eoc cs rd db0-db7 t power-up t 1 valid data power down here figure 21. mode 2 operation
ad7822/ad7825/ad7829 C13C rev. a parallel interface the parallel interface of the ad7822, ad7825, and ad7829 is eight bits wide. figure 22 shows a timing diagram illustrating the operational sequence of the ad7822/ad7825/ad7829 parallel interface. the multiplexer address is latched into the ad7822/ad7825/ad7829 on the fall ing edge of the rd input. the on-chip track/hold goes into hold mode on the falling edge of convst and a conversion is also initiated at this point. when the conversion is complete, the end of conversion line ( eoc ) pulses low to indicate that new data is available in the output register of the ad7822, ad7825, and ad7829. the eoc pulse will stay logic low for a maximum time of 110 ns. however, the eoc pulse can be reset high by a rising edge of convst eoc cs rd db0-db7 a0-a2 t 1 t 4 t 5 t 6 t 7 t 8 t 3 t 9 t 10 t 11 t 12 t 13 valid data next channel address t 2 figure 22. ad7822/ad7825/ad7829 parallel port timing rd . this eoc line can be used to drive an edge-triggered inter- rupt of a microprocessor. cs and rd going low accesses the 8-bit conversion result. it is possible to tie cs permanently low and use only rd to access the data. in systems where the part is interfaced to a gate array or asic, this eoc pulse can be applied to the cs and rd inputs to latch data out of the ad7822, ad7825, and ad7829 and into the gate array or asic. this means that the gate array or asic does not need any conver- sion status recognition logic and it also eliminates the logic required in the g ate array or asic to generate the read signal for the ad7822, ad7825, and ad7829.
ad7822/ad7825/ad7829 C14C rev. a microprocessor interfacing the parallel port on the ad7822/ad7825/ad7829 allows the adcs to be interfaced to a range of many different micro- controllers. this section explains how to interface the ad7822, ad7825, and ad7829 with some of the more common micro- controller parallel interface protocols. ad7822/ad7825/ad7829 to 8051 figure 23 below shows a parallel interface between the ad7822, ad7825, and ad7829 and the 8051 microcontroller. the eoc signal on the ad7822, ad7825, and ad7829 provides an inter- rupt request to the 8051 when a conversion ends and data is ready. port 0 of the 8051 may serve as an input or output port, or as in this case when used together, may be used as a bidirec- tional low order address and data bus. the address latch enable output of the 8051 is used to latch the low byte of the address during accesses to the device, while the high order address byte is supplied from port 2. port 2 latches remain stable when the ad7822, ad7825, and ad7829 are addressed, as they do not have to be turned around (set to 1) for data input as is the case for port 0. ad0-ad7 ale a8-a15 rd int 8051* latch decoder db0-db7 rd eoc cs *additional pins omitted for clarity ad7822/ ad7825/ ad7829* figure 23. interfacing to the 8051 ad7822/ad7825/ad7829 to pic16c6x/7x figure 24 shows a parallel inter face between the ad7822, ad7825, and ad7829 and the pic16c64/65/74. the eoc signal on the ad7822, ad7825, and ad7829 provides an interrupt request to the microcontroller when a conversion begins. of the pic16c6x/7x range of microcontrollers only the pic16c64/65/74 can provide the option of a parallel slave port. port d of the microcontroller will operate as an 8-bit wide parallel slave port when control bit pspmode in the trise register is set. setting pspmode enables the port pin re0 to be the rd output and re2 to be the cs (chip select) output. for this functionality, the corresponding data direction bits of the trise register must be configured as outputs (reset to 0). see pic16/17 microcontroller user manual. psp0-psp7 rd int pic16c6x/7x* db0-db7 rd eoc cs *additional pins omitted for clarity cs ad7822/ ad7825/ ad7829* figure 24. interfacing to the pic16c6x/7x ad7822/ad7825/ad7829 to adsp-21xx figure 25 below shows a parallel interface between the ad 7822, ad7825, and ad7829 and the adsp-21xx series of dsps. as before, the eoc signal on the ad7822, ad7825, and ad7829 provides an interrupt request to the dsp when a conversion ends. d7-d0 rd irq adsp-21xx* db0-db7 rd eoc cs *additional pins omitted for clarity dms en address decode logic a13-a0 ad7822/ ad7825/ ad7829* figure 25. interfacing to the adsp-21xx
ad7822/ad7825/ad7829 C15C rev. a interfacing multiplexer address inputs figure 26 shows a simplified interfacing scheme between the ad7825/ad7829 and any microprocessor or microcontroller, which facilitates easy channel selection on the adcs. the mul- tiplexer address is latched on the falling edge of the rd signal, as outlined in the parallel interface section, which allows the use of the 3 lsbs of the address bus to select the channel address. as shown in figure 26, only address bits a3 to a15 are address decoded allowing a0 to a2 to be changed according to desired channel selection without affecting chip selection. ad7825/ ad7829 a0 a1 a2 cs rd db7-db0 a15-a3 cs rd db0-db7 a15-a3 a2-a0 adc i/o address mux address a/d result mux address (channel selection a0-a2) latched microprocessor read cycle address decode system bus figure 26. ad7825/ad7829 simplified micro interfacing scheme convst rd cs eoc db7-db0 ad7822 dsp/ latch/asic convst eoc rd cs db0-db7 a/d result t 1 t 4 figure 27. ad7822 stand-alone operation the ad7822, being the single channel device, does not have any multiplexer addressing associated with it and can in fact be controlled with just one signal, i.e., the convst signal. as shown in figure 27 the rd and cs pins are both tied to the eoc pin and the resulting signal may be used as an interrupt request signal (irq) on a dsp, as a wr signal to memory or as a clk to a latch or asic. the timing for this interface, as shown in figure 27, demonstrates how with the convst signal alone, a conversion may be initiated, data is latched out and the operating mode of the ad7822 can be selected.
ad7822/ad7825/ad7829 C16C rev. a 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead small outline package (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc
ad7822/ad7825/ad7829 C17C rev. a 24-lead plastic dip (n-24) 24 112 13 0.280 (7.11) 0.240 (6.10) pin 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) min 0.200 (5.05) 0.125 (3.18) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 24-lead small outline package (r-24) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc
ad7822/ad7825/ad7829 C18C rev. a 28-lead plastic dip (n-28) 28 1 14 15 1.565 (39.70) 1.380 (35.10) pin 1 0.580 (14.73) 0.485 (12.32) 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) min seating plane 0.250 (6.35) max 0.100 (2.54) bsc 0.070 (1.77) max 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 28-lead small outline package (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc

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